Background of LPC

Low Pin Count, or LPC, was introduced by Intel in 1998 as an interface to connect low-bandwidth devices to the CPU. It had replaced its Industry Standard Architecture (ISA) counterpart improving the data rate transfer from 8 MHz up to 33 MHz. LPC transfers data using a 4-bit bus and features an architecture using a minimum of seven signals, reducing the numbers of pins required on peripheral chips and the amount of traffic on the motherboard.

LPC specification requires seven signals:

• Four serial LAD[3:0] signals for carrying multiplexed data including cycle type, cycle direction, chip selection, address, data, and wait times
• One LCLK clock signal of 33 MHz provided by the host
• One LFRAME# for indicating the start or stop of a transaction
• One LRESET# for performing bus resets

An additional six sideband signals can optionally be included to communicate interrupts and manage power; if used, this would make a total of thirteen signals. These signals include:

• LDRQ# for encoded DMA/bus master request
• ERIRQ for peripherals that require interrupt support
• CLKRUN# clock signal for peripherals that need DMA or bus mastering in a system that can stop the PCI bus
• LPME# for peripherals that want to request wake-up from a low-power state
• LPCPD# for power down
• LSMI# for when a peripheral wants to cause SMI# on an I/O instruction for retry

When set up, the LPC interface is commonly connected through a host device to a PCI or host bus. Peripherals are connected downstream on the LPC interface including super I/O components, flash, and other embedded controllers. LPC operates using cycle types that predominantly function the same for memory, I/O, DMA, and bus master devices (firmware memory including BIOS would operate in a slightly different way).

For memory, I/O, DMA, and bus master cycle types, the host would initiate the operation using the LFRAME# signal. The host would then supply the necessary information on the LAD[3:0] signal lines, which can include the transfer type (memory, I/O, DMA), transfer direction (read/write), address, data, wait states, DMA channel, and bus master grant. The host determines completion of the cycle by turning the bus around to the peripheral, where the peripheral sends the host applicable data values and turns the bus back around to indicate the cycle is complete.

Limitations of LPC

To meet the growing demand of newer devices, in 2013 Intel went further to create a new, more cost-effective protocol that also delivered a higher performance. eSPI is considered to be a replacement and successor to the LPC interface.

LPC has a few limitations that led the way to the development of eSPI including:

• Its incorporation of up to 13 pins (7 required and 6 optional sideband signals), increasing pin cost
• Its requisite of 3.3V IO signaling technology, increasing costs
• Its lower bandwidth and bus clock frequency of 33 MHz

Background of eSPI

Before we discuss more on the reasons behind why eSPI replaces LPC, let’s get more familiar with the eSPI protocol:

eSPI is a serial bus interface for client and server platforms that is based on SPI, using the same master and slave topology but operates with a different protocol to meet new requirements.

For instance, eSPI uses I/O, or input/output, communication, instead of MOSI/MISO used in SPI. It also includes a transaction layer on top of the SPI protocol, defining packets such as command and response packets that allow both the master and slave to initiate alert and reset signals. eSPI supports communication between Embedded Controller (EC), Baseboard Management Controller (BMC), Super-I/O (SIO) and Port-80 debug cards.

eSPI uses Peripheral, Virtual Wire, Out of Band, and Flash Access channels to communicate different sets of data.

• The Peripheral Channel is used for communication between eSPI host bridge located on the master side and eSPI endpoints located on the slave side. LPC Host and LPC Peripherals are an example of eSPI host bridge and eSPI endpoints respectively.
• Virtual Wire Channel: The Virtual Wire channel is used to communicate the state of sideband pins or GPIO tunneled through eSPI as in-band messages. Serial IRQ interrupts are communicated through this channel as in-band messages.
• OOB Channel: The SMBus packets are tunneled through eSPI as Out-Of-Band (OOB) messages. The whole SMBus packet is embedded inside the eSPI OOB message as data.
• Flash Access Channel: The Flash Access channel provides a path allowing the flash components to be shared run-time between chipset and the eSPI slaves that require flash accesses such as EC (Embedded Controller) and BMC.

How eSPI Improves Upon the LPC Interface

Some of the major improvements that eSPI addresses is its reduction of the number of pins on the motherboard, the increased throughput up to 66 MHz, and the decreased voltage to 1.8V.

The eSPI protocol is able to reduce the number of pins on the motherboard by removing the sideband pins and converting chipset and slave devices into in-band messages. Also, a maximum of eight pins are to be used for one slave, including the chip select, clock, four data lines, alert and reset. For fully optimized bandwidth, eSPI allows for scalable bandwidth to determine the best balance between power and performance based on the application, while the accelerated clock speed of up to 66 MHz also improves the bandwidth for data transfers. The master must support single/dual/quad I/O modes and 20/25/33/50/66 MHz, while the slave must support single I/O mode at 20 MHz minimum. To achieve a lower voltage, eSPI uses the same I/O buffer as SPI, allowing it to support the 1.8V.

How Total Phase Supports eSPI Protocol Analysis

eSPI is becoming a widely used protocol in embedded systems, supporting communication between Embedded Controllers (EC), Baseboard Management Controllers (BMC), and Super-I/O (SIO), replacing the need for LPC. Total Phase offers a solution to debug eSPI traffic in real time using the Promira Serial Platform with the eSPI Analysis Application. This eSPI application allows users to monitor eSPI communication between multiple eSPI devices and can even be configured to emulate an eSPI master, as noted here. Used within Total Phase’s Data Center Software, users can:

• Monitor communication between a master and slaves on data lines
• Support single, dual and quad I/O
• Support clock speeds up to 66MHz
• Monitor up to 5 channels (peripheral, virtual wire, OOB, Flash, Independent)
• Monitor up to 2 slave select lines
• Monitor 2 alert lines
• Monitor 2 reset lines
• Match triggers, hardware filters and statistics

For more information about the eSPI Analysis Application, contact us at sales@totalphase.com.